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rev.3.00 jul 07, 2005 page 1 of 11 HD74LVC2G53 2?channel analog multiplexer/demultiplexer rej03d0156?0300 rev.3.00 jul.07.2005 description the HD74LVC2G53 has 2?channel analog multiplexer/demultiplexer in an 8 pin package. applications include signal gating, chopping, modulation, or demodulation (modem), and signal multiplexing for analog to digital and digital to analog conversion systems. low voltage and high-speed operation is suitable for the battery powered products (e.g., notebook computers), and the low power consumption extends the battery life. features ? the basic gate function is lined up as renesas uni logic series. ? supply voltage range: 1.65 to 5.5 v ? operating temperature range: ?40 to +85c ? control inputs: vih (max.) = 5.5 v (@vcc = 0 v to 5.5 v) ? ordering information part name package type package code (previous code) package abbreviation taping abbreviation (quantity) HD74LVC2G53cpe sxbg0008ka-a (tbs-8v) cp HD74LVC2G53cle wcsp-8 pin sxbg0008kb-a (tbs-8av) cl e (3,000 pcs/reel) article indication e 5 3 y m marking year code month code function table control inputs inh a on channel h x none l h y 1 l l y 0 h : high level l : low level x : immaterial package code (previous code) package abbreviation sxbg0008ka-a (tbs-8v) cp sxbg0008kb-a (tbs-8av) cl e 5 3 y m marking
HD74LVC2G53 rev.3.00 jul 07, 2005 page 2 of 11 pin arrangement (bottom view) (top view) a 27 3 45 gnd height 0.5 mm 0.5 mm pitch 0.17 mm 8?ball (cp) 0.23 mm 8?ball (cl) 0.9 mm 1.9 mm gnd y 1 inh y 0 6 18 com v cc pin#1 index logic diagram a 5 2 17 6 inh com c io c io y 1 y 0 (top view) 17 com
HD74LVC2G53 rev.3.00 jul 07, 2005 page 3 of 11 absolute maximum ratings item symbol ratings unit test conditions supply voltage range v cc ?0.5 to 6.5 v input voltage range *1 v i ?0.5 to 6.5 v output voltage range *1, 2 v o ?0.5 to v cc +0.5 v output : h or l input clamp current i ik ?50 ma v i < 0 output clamp current i ok ?50 ma v o < 0 continuous output current i o 50 ma v o = 0 to v cc continuous current through v cc or gnd i cc or i gnd 100 ma 140 cp package thermal impedance ja 102 c/w cl storage temperature tstg ?65 to 150 c notes: the absolute maximum ratings are values, which must not individually be exceeded, and furthermore no two of which may be realized at the same time. 1. the input and output voltage rati ngs may be exceeded if the input and output clamp-current ratings are observed. 2. this value is limited to 5.5 v maximum. recommended operating conditions item symbol min max unit conditions supply voltage range v cc 1.65 5.5 v input voltage range v i 0 5.5 v output voltage range v o 0 v cc v 0 20 v cc = 1.65 to 1.95 v, 2.3 to 2.7 v 0 10 v cc = 3.0 to 3.6 v input transition rise or fall rate ? t / ? v 0 10 ns / v v cc = 4.5 to 5.5 v operating free-air temperature t a ?40 85 c note: unused or floating inputs must be held high or low. item symbol min max unit conditions 1.65 5.5 v 0 5.5 v 0 v cc v 0 20 0 10 v 0 10 ns / v operating free-air temperature t a ?40 85 c note: unused or floating inputs must be held high or low.
HD74LVC2G53 rev.3.00 jul 07, 2005 page 4 of 11 electrical characteristics ? ta = ?40 to 85c item symbol v cc (v) min typ max unit test condition 1.65 to 1.95 v cc 0.65 ? ? 2.3 to 2.7 v cc 0.7 ? ? 3.0 to 3.6 v cc 0.7 ? ? v ih 4.5 to 5.5 v cc 0.7 ? ? 1.65 to 1.95 ? ? v cc 0.35 2.3 to 2.7 ? ? v cc 0.3 3.0 to 3.6 ? ? v cc 0.3 input voltage v il 4.5 to 5.5 ? ? v cc 0.3 v control input only. 1.65 ? 13 30 i s = 4 ma 2.3 ? 10 20 i s = 8 ma 3.0 ? 8.5 17 i s = 24 ma on?state switch resistance r on 4.5 ? 6.5 13 i s = 32 ma v i =v cc or gnd 1.65 ? 86.5 120 i s = 4 ma 2.3 ? 23 30 i s = 8 ma 3.0 ? 13 20 i s = 24 ma peak on resistance r on (p) 4.5 ? 8 15 i s = 32 ma v i =v cc to gnd 1.65 ? ? 7 i s = 4 ma 2.3 ? ? 5 i s = 8 ma 3.0 ? ? 3 i s = 24 ma difference of on-state resistance between switches ? r on 4.5 ? ? 2 ? i s = 32 ma v i =v cc to gnd ? ? 1.0 off-state switch leakage current i s (off) 5.5 ? ? 0.1* 1 a v i = v cc and v o = gnd or v i = gnd and v o = v cc , v inh = v ih ? ? 1.0 on-state switch leakage current i s (on) 5.5 ? ? 0.1* 1 a v i = v cc or gnd, v inh = v il v o = open ? ? 1.0 control input current i in 5.5 ? ? 0.1* 1 a v in = v cc or gnd ? ? 10 i cc 5.5 ? ? 1.0* 1 a v in = v cc or gnd quiescent supply current ? i cc 5.5 ? ? 500 a v c = v cc ?0.6 v control input capacitance c ic 5.0 ? 3.5 ? pf ? 6.5 ? y c i/o(off) 5.0 ? 10 ? com switch terminal capacitance c i/o(on) 5.0 ? 14.0 ? pf note: 1. ta = 25c 1.65 ? 86.5 120 i 2.3 ? 23 30 i 3.0 ? 13 20 i 4.5 ? 8 15 i s 1.65 ? ? 7 i s = 4 ma 2.3 ? ? 5 i s = 8 ma 3.0 ? ? 3 i 4.5 ? ? 2 ? ? 1.0 ? ? 0.1* 1 a ? ? 1.0 ? ? 0.1* ? ? 1.0 5.5 ? ? 0.1* ? ? 10 5.5 5.5 ? ? 1.0* ? i cc 5.5 ? ? 500 c ic 5.0 ? 3.5 ? pf 5.0
HD74LVC2G53 rev.3.00 jul 07, 2005 page 5 of 11 switching characteristics ? v cc = 1.8 0.15 v ta = ?40 to 85c item symbol min max unit test conditions from (input) to (output) propagation delay time* 1 t plh , t phl ? 2.0 c l = 30 pf, r l = 1.0 k ? com or yn yn or com enable time t zh , t zl 3.3 9.0 c l = 30 pf, r l = 1.0 k ? inh com or yn disable time t hz , t lz 3.2 10.9 c l = 30 pf, r l = 1.0 k ? inh com or yn enable time t zh , t zl 2.9 10.3 c l = 30 pf, r l = 1.0 k ? a yn disable time t hz , t lz 2.1 9.4 ns c l = 30 pf, r l = 1.0 k ? a yn ? v cc = 2.5 0.2 v ta = ?40 to 85c item symbol min max unit test conditions from (input) to (output) propagation delay time* 1 t plh , t phl ? 1.2 c l = 30 pf, r l = 500 ? com or yn yn or com enable time t zh , t zl 2.5 6.1 c l = 30 pf, r l = 500 ? inh com or yn disable time t hz , t lz 2.3 9.3 c l = 30 pf, r l = 500 ? inh com or yn enable time t zh , t zl 2.1 7.2 c l = 30 pf, r l = 500 ? a yn disable time t hz , t lz 1.4 7.9 ns c l = 30 pf, r l = 500 ? a yn ? v cc = 3.3 0.3 v ta = ?40 to 85c item symbol min max unit test conditions from (input) to (output) propagation delay time* 1 t plh , t phl ? 0.8 c l = 50 pf, r l = 500 ? com or yn yn or com enable time t zh , t zl 2.2 5.4 c l = 50 pf, r l = 500 ? inh com or yn disable time t hz , t lz 2.3 8.1 c l = 50 pf, r l = 500 ? inh com or yn enable time t zh , t zl 1.9 5.8 c l = 50 pf, r l = 500 ? a yn disable time t hz , t lz 1.1 7.2 ns c l = 50 pf, r l = 500 ? a yn ? v cc = 5.0 0.5 v ta = ?40 to 85c item symbol min max unit test conditions from (input) to (output) propagation delay time* 1 t plh , t phl ? 0.6 c l = 50 pf, r l = 500 ? com or yn yn or com enable time t zh , t zl 1.8 4.5 c l = 50 pf, r l = 500 ? inh com or yn disable time t hz , t lz 1.6 8.0 c l = 50 pf, r l = 500 ? inh com or yn enable time t zh , t zl 1.3 5.4 c l = 50 pf, r l = 500 ? a yn disable time t hz , t lz 1.0 5.0 ns c l = 50 pf, r l = 500 ? a yn notes: 1. the propagation delay is calculated rc time const ant of typical on-state resist ance of the switch and the specified load capacitance, when driven by an ideal voltage sour ce (zero output impedance). = 30 pf, r l = 500 = 30 pf, r l = 500 l = 30 pf, r l = 500 ? a yn unit test conditions 0.8 c l = 50 pf, r l = 500 2.2 5.4 c l = 50 pf, r 2.3 8.1 c l = 50 pf, r 1.9 5.8 c l = 50 pf, r 1.1 7.2 0.8 c ns 0.8 c c ta = ?40 to 85c symbol min max propagation delay time* 1 t plh , t phl ? t zh , t zl 1.8 4.5 c t hz , t lz 1.6 8.0 c , t zl 1.3 5.4 c 1.0 5.0
HD74LVC2G53 rev.3.00 jul 07, 2005 page 6 of 11 analog switch characteristics ta = 25c item v cc (v) min typ max unit test conditions from (input) to (output) 1.65 ? 35 ? 2.3 ? 120 ? 3.0 ? 190 ? 4.5 ? 215 ? c l = 50 pf, r l = 600 ? 1.65 ? >300 ? 2.3 ? >300 ? 3.0 ? >300 ? frequency response (switch on) 4.5 ? >300 ? mhz c l = 5 pf, r l = 50 ? adjust fin voltage to obtain 0dbm at output when fin is 1mhz (sine wave). increase fin frequency until the db?meter reads ?3 dbm. 20 log(v o /v i )= ?3 dbm com or y y or com 1.65 ? ?58 ? 2.3 ? ?58 ? 3.0 ? ?58 ? 4.5 ? ?58 ? c l = 50 pf, r l = 600 ? 1.65 ? ?42 ? 2.3 ? ?42 ? 3.0 ? ?42 ? crosstalk (between switches) 4.5 ? ?42 ? db c l = 5 pf, r l = 50 ? adjust fin voltage to obtain 0dbm at input when fin is 1mhz (sine wave). com y 1.65 ? 35 ? 2.3 ? 50 ? 3.0 ? 70 ? crosstalk (control input to signal output) 4.5 ? 100 ? mv c l = 50 pf, r l = 600 ? adjust rl value to obtain 0a at i in/out when fin is 1mhz (square wave) inh com or y 1.65 ? ?60 ? 2.3 ? ?60 ? 3.0 ? ?60 ? 4.5 ? ?60 ? c l = 50 pf, r l = 600 ? 1.65 ? ?50 ? 2.3 ? ?50 ? 3.0 ? ?50 ? feed through attenuation (switch off) 4.5 ? ?50 ? db c l = 5 pf, r l = 50 ? adjust fin voltage to obtain 0dbm at input when fin is 1mhz (sine?wave) com or y y or com 1.65 ? 0.1 ? 2.3 ? 0.025 ? 3.0 ? 0.015 ? 4.5 ? 0.01 ? c l = 50 pf, r l = 10 k ? fin = 1khz (sine?wave) 1.65 ? 0.15 ? 2.3 ? 0.025 ? 3.0 ? 0.015 ? sine?wave distortion 4.5 ? 0.01 ? % c l = 50 pf, r l = 10 k ? fin = 10khz (sine?wave) v i =1.4v p?p , v cc =1.65v v i =2.0v p?p , v cc =2.3v v i =2.5v p?p , v cc =3.0v v i =4.0v p?p , v cc =4.5v com or y y or com operating characteristics ta = 25c item symbol v cc (v) min typ max unit test conditions 1.8 ? 9 ? 2.5 ? 10 ? 3.3 ? 10 ? power dissipation capacitance c pd 5.0 ? 12 ? pf f = 10 mhz adjust rl value to obtain 0a at i in/out when fin is 1mhz (square wave) l = 50 pf, r l = 600 ? 1.65 ? ?50 ? 2.3 ? ?50 ? 3.0 ? ?50 ? 4.5 ? ?50 ? c l = 5 pf, r l = 50 ? adjust fin voltage to obtain 0dbm at input when fin is 1mhz (sine?wave) 1.65 ? 0.1 ? 1.65 ? 0.1 ? 2.3 ? 0.025 ? 3.0 ? 0.015 ? 4.5 ? 0.01 ? c l = 50 pf, r l = 10 k fin = 1khz 1.65 ? 0.15 ? 2.3 ? 0.025 ? 3.0 ? 0.015 ? 4.5 ? 0.01 ? %
HD74LVC2G53 rev.3.00 jul 07, 2005 page 7 of 11 test circuit v out v cc +? v cc y 0 or y 1 gnd com (on) v v a = v il or v ih v inh = v il v =v ? r on in cc i s v in?out r = on i s (?) v in?out v cc v cc gnd y 0 y 1 com (off) a v =v or gnd in cc v =gnd or v out cc ? i (off), i (on) ss v a = v il or v ih v inh = v ih v cc v cc gnd open y 0 y 1 com (off) a v =v or gnd in cc v out v a = v il or v ih v inh = v il v =gnd or v out v =gnd out v =gnd cc or v cc or v v cc v cc v a v =v or gnd in cc v =v in cc v =v v a = v a = v a il or v ih v inh = v il
HD74LVC2G53 rev.3.00 jul 07, 2005 page 8 of 11 test circuit (cont.) open open test s1 vtt vtt s1 c l r l r l gnd gnd t / t plh phl t / t zh hz t / t zl lz 1.80.15 2.50.2 3.30.3 5.00.5 inputs v cc (v) v cc 2 v cc 2 v cc 2 v cc 2 v cc v cc / 2 v cc / 2 v cc / 2 v cc / 2 v cc v cc v cc v i v ref c l r l ?v vtt t r / t f 500 ? 0.15 v 0.15 v 0.3 v 0.3 v 500 ? 500 ? 1.0 k? load circuit from output 2 ns 2 ns 2.5 ns 2.5 ns 30 pf 30 pf 50 pf 50 pf v ref v ref v ref v ref v i 0 v t plh v t phl oh v ol input output v oh v ol control input v ref v ref v ref v oh ? ?v v ol + ?v v ref v i v oh 0 v v ol t hz t lz t zh t zl output (waveform ? a) output (waveform ? b) notes: 1. c l includes probe and jig capacitance. 2. waveform?a is for an output with internal conditions such that the output is low except when disabled by the output control. 3. waveform?b is for an output with internal conditions such that the output is high except when disabled by the output control. 4. all input pulses are supplied by generators having the following characteristics: prr 10mhz, zo = 50 ?. 5. the output are measured one at a time with one transition per measurement. v ref t phl v ref v ref t zh t zl
HD74LVC2G53 rev.3.00 jul 07, 2005 page 9 of 11 frequency response (switch on) v cc 0.1 f v in v out v cc f in f = sine wave in gnd y 0 y 1 com (on) c = 50 pf l r = 600 l ? r = 50 l ? v /2 cc crosstalk (between any switches) v cc 0.1 f v in v out1 v /2 cc v cc f in gnd com y 0 y 1 (on) c = 50 pf or 5 pf l c = 50 pf or 5 pf l r = 600 or 50 l ? ? r = 600 or 50 l ? ? r = 600 or 50 l ? ? r = 50 l ? v cc v out2 v /2 cc v cc gnd (off) or 50 ? or 5 pf v a = v il or v ih v inh = v il v a = v il or v ih v inh = v il v /2 cc v /2 cc v /2 y 1 c = 50 pf or 5 pf l c = 50 pf or 5 pf l c = 50 pf or 5 pf r = 600 or 50 l r = 600 l r = 600 ? ? v cc v cc v v cc v cc v gnd (off)
HD74LVC2G53 rev.3.00 jul 07, 2005 page 10 of 11 feedthrough attenuation (switch off) v cc 0.1 f v in v out v /2 cc v cc f in gnd (off) c = 50 pf or 5 pf l r = 600 l ? ? v /2 cc r = 600 l ? r = 50 l ? 600 ? crosstalk (control input to signal output) v out v /2 cc c = 50 pf l r = 600 l ? v /2 cc r = 600 l ? v cc v inh v cc gnd com com com y 0 y 1 y 0 y 1 y 0 y 1 r = 50 l ? sine-wave distortion v cc 10 f v in v out v /2 cc v cc f in gnd 10 f (on) c = 50 pf l r = 10 k l ? or 50 ? or 50 v a = v il or v ih v a = v il or v ih v inh = v il v a = v il or v ih v inh = v il v out v /2 cc v /2 cc v /2 c = 50 pf or 5 pf l c = 50 pf or 5 pf l c = 50 pf or 5 pf r = 600 l r = l r = ? ? 600 ? com y 0 y v cc v cc v 10 f v in v in v v cc v cc v gnd (on) or 50 or v ih = v il
HD74LVC2G53 rev.3.00 jul 07, 2005 page 11 of 11 package dimensions d c b 2 1 a pin#1 index area 1 y c c yc seating plane a b 0.20 0.05 0.50 0.90 a 2 0.50 tbs-8v renesas code jeita package code previous code max nom min dimension in millimeters symbol reference 0.19 0.20 0.35 0.05 0.20 0.0014g mass[typ.] 1 z y x d a a e e z b s-xfbga8-0.9x1.9-0.50 sxbg0008ka-a 1 y 0.10 0.15 0.17 0.15 1.90 e d cab c b8 m m d e 1 2 a a d e a e z z e sxbg0008kb-a s-xfbga8-0.9x1.9-0.50 mass[typ.] 0.0015g previous code jeita package code renesas code tbs-8av 0.20 0.05 0.50 0.90 a 2 0.50 max nom min dimension in millimeters symbol reference 0.25 0.20 (0.315) 0.05 0.20 1 z y x d a a e e z b 1 y 0.155 0.185 0.20 1.90 * e d d c b 2 1 a pin#1 index area 1 y c c yc seating plane a b * reference value. cab c b8 m m d e 1 2 a a d e a e z z e cab cab c b8 b8 b8 b8 b8 m m mass[typ.] 0.0015g previous code tbs-8av d e z
keep safety first in your circuit designs! 1. renesas technology corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. notes regarding these materials 1. these materials are intended as a reference to assist our customers in the selection of the renesas technology corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to renesas technology corp. or a third party. 2. renesas technology corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by renesas technology corp. without notice due to product improvements or other reasons. it is therefore recommended that customers contact renesas technology corp. or an authorized renesas technology corp. product distributor for the latest product information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. renesas technology corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. please also pay attention to information published by renesas technology corp. by various means, including the renesas technology corp. semiconductor home page (http://www.renesas.com). 4. when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. renesas technology corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. renesas technology corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. please contact renesas technology corp. or an authorized renesas technology corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. the prior written approval of renesas technology corp. is necessary to reprint or reproduce in whole or in part these materials. 7. if these products or technologies are subject to the japanese export control restrictions, they must be exported under a license from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is prohibited. 8. please contact renesas technology corp. for further details on these materials or the products contained therein. sales strategic planning div. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan http://www.renesas.com refer to "http://www.renesas.com/en/network " for the latest and detailed information. renesas technology america, inc. 450 holger way, san jose, ca 95134-1368, u.s.a tel: <1> (408) 382-7500, fax: <1> (408) 382-7501 renesas technology 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menara amcorp, amcorp trade centre, no.18, jalan persiaran barat, 46050 petaling jaya, selangor darul ehsan, malaysia tel: <603> 7955-9390, fax: <603> 7955-9510 renesas sales offices ? 2005. renesas technology corp., all rights reserved. printed in japan. colophon .3.0 1. these materials are intended as a reference to assist our customers in the selection of the renesas technology corp. product application; they do not convey any license under any intellectual property rights, or any other rights, belonging to renesas t 2. renesas technology corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating 3. all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents i nformation on products at the time of publication of these materials, and are subject to change by renesas technology corp. without notice due to product improvement therefore recommended that customers contact renesas technology corp. or an authorized renesas technology corp. product distrib renesas technology corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies o r errors. please also pay attention to information published by renesas technology corp. by various means, including the renesas techn ology corp. semiconductor 4. when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, a nd algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. renesas technology corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. renesas technology corp. semiconductors are not designed or manufactured for use in a device or system that is used under ci is potentially at stake. please contact renesas technology corp. or an authorized renesas technology corp. product distributor product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerosp 6. the prior written approval of renesas technology corp. is necessary to reprint or reproduce in whole or in part these materi 7. if these products or technologies are subject to the japanese export control restrictions, they must be exported under a lic cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is 8. please contact renesas technology corp. for further details on these materials or the products contained therein. http://www.renesas.com/en/network " for the latest and detailed information. renesas technology america, inc. 450 holger way, san jose, ca 95134-1368, u.s.a tel: <1> (408) 382-7500, fax: <1> (408) 382-7501 renesas technology europe limited dukes meadow, millboard road, bourne end, buckinghamshire, sl8 5fh, u.k. tel: <44> (1628) 585-100, fax: <44> (1628) 585-900 hong kong ltd. 7th floor, north tower, world finance centre, harbour city, 1 canton road, tsimshatsui, kowloon, hong kong tel: <852> 2265-6688, fax: <852> 2730-6071 renesas sales offices

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